This application claims priority to Indian Application No. 2639/DEL/2011 filed 12 Sep. 2011, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
This invention relates to the field of data processing systems. More particularly, this invention relates to circuits and methods for storing data in operational and sleep modes.
2. Description of the Prior Art
Conventional sense amplifier latches that receive and output data in response to a clock signal are known. Conventionally these storage circuits receive a data signal and an inverse data signal and store and output these signals on two data lines. Such data storage latches have a precharge cycle in a first half of the clock cycle in which both output lines are precharged, then on the edge of the clock signal the data signal is captured and it is then held for the second half of the clock cycle. A problem with such a circuit is that during the next precharge phase the data that was previously held is lost. Thus, in order for such a latch to function in a useful manner it has conventionally been used as a master latch in a master slave flip flop, the data being transferred to the slave latch before it is lost. It can then be output from the slave latch and the master latch can be precharged again prior to receiving the next data value input.
In some systems sense amplifier latches can be used as the master with a set reset latch acting as the slave latch.
A disadvantage of such an arrangement is that sense amplifier latches are dual rail systems and as such tend to have high power consumption due to the discharge of one of the rails. Furthermore, they generally have significant topological restraints. However, they have the advantage of robust performance with high data slew due to the dual rail data input.
Furthermore, when they are powered down and the clock signal turned off they generally lose the data that they store. Providing them with a data retention capability such that they can retain data in low power mode using perhaps an associated balloon latch has a considerable circuit area impact. For this reason such flip flops provided with such a retention capability are not suitable for use in a standard cell library.
It would be advantageous to produce a robust latching device with differential data inputs but reduced topological restraints. It would also be desirable in some embodiments to be able to provide a flip flop that has a low power retention capability and a size and architecture such that it can be configured as a standard cell in a standard cell library.